The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor memory device, such as a DRAM (dynamic random access memory) or a clock synchronous DRAM, capable of facilitating the timing control of output signals.
This application is based on Japanese Patent Application No. 9-249778, filed Aug. 30, 1997, the content of which is incorporated herein by reference.
FIG. 1 is a system block diagram of a semiconductor memory device (clock synchronous DRAM) as an example of a conventional semiconductor integrated circuit device formed on a semiconductor substrate. The semiconductor memory device is mainly made of a memory cell array 3, in which a large number of memory cells are arranged in a matrix. A memory cell is the smallest unit of storage. The memory cell array 3 comprises word lines for selecting memory cells in the direction of row, bit lines for selecting memory cells in the direction of column, a row decoder for receiving a row address input signal and selecting a word line, a column decoder for receiving a column address input signal and selecting a bit line, and a sense amplifier for amplifying data stored in the accessed memory cell and transferred to a bit line.
In a DRAM or a clock synchronous DRAM, the signals flow as follows. The address signal is input from the input terminal to the memory cell array 3 in synchronization with the row and column select signals in a time-division manner and latched in each of the row and column address buffers. The row decoder selects and drives a word line, thereby accessing a memory cell. The data in the accessed memory cell is transferred to a bit line (data line). The data is amplified by the sense amplifier as well as written into the memory cell again. Next, the column decoder selects the output of the sense amplifier. The selected data is transferred to a data output circuit 4 via the bit line. To prevent the data in the memory cells from being destroyed, the series of operations is controlled by an internal synchronous signal and carried out in a predetermined sequence or timing.
The semiconductor memory device further comprises an input receiver circuit 1 that receives an externally supplied input signal and a control circuit 2, in addition to the above-described basic configuration (the memory cell array).
The data output circuit 4 will be explained in detail.
FIG. 2 is a functional block diagram of the data output circuit 4. The data output circuit 4 comprises a data transfer circuit 11 that receives the data read from the memory and appearing in a read signal RD, an equalizing circuit 12 to which the output of the data transfer circuit 11 is input, and an output buffer 13 to which the output of the equalizing circuit 12 is input and outputs an output signal DQ. The data transfer circuit 11 transfers the read signal RD in synchronization with an output clock OUTCLK. The equalizing circuit 12 operates in synchronization with an equalize signal EQ. During operations other than the read operation caused by a burst operation, the equalizing circuit 12 turns off the inverters in the data transfer paths and equalizes the data paths. The output buffer 13 brings the output terminal into one of the high level, low level, and high-impedance level according to the data transferred from the equalizing circuit 12 in synchronization with the equalize signal EQ.
FIG. 3 is a detailed circuit diagram of the data output circuit 4.
The output buffer 13 comprises a PMOS transistor 5 whose source is connected to a power-supply voltage Vcc and an NMOS transistor 6 whose source is connected to the ground Vss and whose drain is connected to the drain of the PMOS transistor 5. The drain of the PMOS transistor 5 and that of the NMOS transistor 6 are connected to an output terminal DQ.
An inverter 22 has its output connected to the gate of the PMOS transistor 5 and its input connected to the output of a clocked inverter 41. The input of the clocked inverter 41 is connected to the output of an inverter 24, to which the read signal RD is input. The drain of a PMOS transistor 9 is connected to a node #3 between the inverter 22 and PMOS transistor 5. The PMOS transistor 9 has its source connected to the power supply Vcc and its gate connected to the output of an inverter 21, to which the equalize signal EQ is input. In the clocked inverter 41, a pair of a PMOS transistor driven by the output clock OUTCLK and an NMOS transistor driven by the inverted signal BOUTCLK is added to an inverter as shown in FIG. 4.
In FIG. 3, an inverter 23 has its output connected to the gate of the NMOS transistor 6 and its input connected to the output of the clocked inverter 41. The drain of an NMOS transistor 10 is connected to a node #4 between the inverter 23 and NMOS transistor 6. The source of the NMOS transistor 10 is connected to the ground Vss. The equalize signal EQ is input to the gate of the NMOS transistor 10.
In FIG. 3, the inverter 24 and clocked inverter 41 constitute the data transfer circuit 11 and the inverters 21, 22 and 23, and transistors 9 and 10 constitute the equalizing circuit 12.
The operation of the data output circuit 4 shown in FIG. 3 will be explained by reference to FIG. 5. FIG. 5 shows the operating waveform of the data output circuit 4 shown in FIG. 3 when the latency=3, the burst length=4, and the data pattern="0101." Latency represents a period of time from a reception of a read command to output of data.
During operations other than the read operation caused by an equalize operation, the equalize signal EQ is high. In this situation, since the inverters 22 and 23 are off and the transistors 9 and 10 are on, the node #3 between the gate of the PMOS transistor 5 and the inverter 22 is high (H) and the node #4 between the gate of the NMOS transistor 6 and the inverter 23 is low (L), making the PMOS transistor 5 and NMOS transistor 6 turn off, which causes the high-impedance (HiZ) level to appear at the output terminal DQ.
When a read command signal is sensed in a first cycle C1 of an external clock CLK, the first bit in the read data is read on the node #1 between the inverter 24 and clocked inverter 41 in a second cycle C2. At this time, the output clock OUTCLK is low, the inverted signal BOUTCLK of the output clock OUTCLK is high, and the clocked inverter 41 is off.
When the output clock OUTCLK becomes high in a third cycle C3, the clocked inverter 41 turns on, causing the data on the node #1 to be transferred to the node #2 between the clocked inverter 41 and the inverters 22 and 23. After the data on the node #1 is transferred to the node #2, the clocks OUTCLK and BOUTCLK become low and high, and the clocked inverter 41 turns off, the next bit in the read data is read on node #1. When the data output circuit 4 is received a read command, the equalize signal EQ remains low during the time when the data output circuit 4 outputs the data in response to the output clocks OUTCLK and BOUTCLK. In the meantime, the inverters 22 and 23 turn on and the transistors 9 and 10 turn off, allowing the data on node #2 to be transferred to nodes #3 and #4, which causes the first data item D1 (="0") in the data pattern to appear at the output terminal DQ.
After a similar operation is repeated with the equalize signal EQ being kept low and the data items for the burst length (that is, four data items) are output, the equalize signal EQ returns to the high level in a seventh cycle C7 of the external clock, making the inverters 22 and 23 turn off and the transistors 9 and 10 turn on, which causes the high impedance level to appear at the output terminal DQ.
Such a conventional data output circuit 4 has the following problems.
The first problem is that the data access time t.sub.AC and the data hold time t.sub.OH differ according to data item or cycle. In the case of the data access time t.sub.AC, data item D1 is output when the equalize signal EQ becomes low, so that the data access time t.sub.AC is determined by the equalize signal EQ. Data item D2 and subsequent ones, however, are output when the output clock OUTCLK becomes high, so that the data access time t.sub.AC is determined by the output clock OUTCLK. As described above, in the conventional data output circuit, the data access time t.sub.AC differs according to the data item. The same holds true for the data hold time t.sub.OH.
When the equalize signal EQ becomes high after the output of data item D4, the output terminal DQ outputs the high impedance, allowing the data hold time t.sub.OH of data item D4 to be determined by the equalize signal EQ. Since data items up to data item D4 are output when the output clock OUTCLK becomes high, the data hold time t.sub.OH for data items before data item D3 is determined by the output OUTCLK, resulting in variations in the data hold time t.sub.OH from cycle to cycle.
The second problem is that the conventional output circuit is difficult to stabilize the variation of the data access time and the data hold time because the timing of each control signal has to coincide with that of the rest. FIG. 6 shows an operating waveform in a case where the timings of the equalize signal EQ and the output clock OUTCLK are shifted from the normal ones. As compared with the proper operation of FIG. 5, the equalize signal EQ becomes low earlier, making the output clock OUTCLK become high, which causes the inverters 22 and 23 to turn on before data item D1 is transferred to the node #2, permitting an invalid data item to be output. To prevent this problem, the equalize signal EQ should be made to become low after the output clock OUTCLK becomes high. Too large a margin, however, would lengthen the data access time t.sub.AC for data item D1, making it difficult to control of the timing of each signal.